1. Field of the Invention
The present invention relates to a thin film magnetic memory device. More particularly, the present invention relates to a randem access memory (RAM) including memory cells having a magnetic tunnel junction (MTJ).
2. Description of the Background Art
An MRAM (Magnetic Random Access Memory) device has attracted attention as a memory device capable of non-volatile data storage with low power consumption. The MRAM device is a memory device that stores data in a non-volatile manner using a plurality of thin film magnetic elements formed in a semiconductor integrated circuit and is capable of random access to each thin film magnetic element.
In particular, recent announcement shows that significant progress in performance of the MRAM device is achieved by using thin film magnetic elements having a magnetic tunnel junction (MTJ) as memory cells. The MRAM device including memory cells having a magnetic tunnel junction is disclosed in technical documents such as xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, Febuary. 2000, and xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elementsxe2x80x9d, ISSCC Digest of Technical Papers, TA7.3, Febuary. 2000.
FIG. 88 is a schematic diagram showing the structure of a memory cell having a magnetic tunnel junction (hereinafter, also simply referred to as xe2x80x9cMTJ memory cellxe2x80x9d).
Referring to FIG. 88, the MTJ memory cell includes a magnetic tunnel junction MTJ having its resistance value valued according to the level of storage data, and an access transistor ATR. The access transistor ATR is formed by a field effect transistor, and is coupled between the magnetic tunnel junction MTJ and ground voltage Vss.
For the MTJ memory cell are provided a write word line WVVL for instructing a data write operation, a read word line RWL for instructing a data read operation, and a bit line BL serving as a data line for transmitting an electric signal corresponding to the level of storage data in the data read and write operations.
FIG. 89 is a conceptual diagram illustrating the data read operation from the MTJ memory cell.
Referring to FIG. 89, the magnetic tunnel junction MTJ has a magnetic layer FL having a fixed magnetic field of a fixed direction (hereinafter, also simply referred to as xe2x80x9cfixed magnetic layer FLxe2x80x9d) , and a magnetic layer VL having a free magnetic field (hereinafter, also simply referred to as xe2x80x9cfree magnetic layer VLxe2x80x9d). A tunnel barrier TB formed from an insulator film is provided between the fixed magnetic layer FL and free magnetic layer VL. According to the level of storage data, either a magnetic field of the same direction as that of the fixed magnetic layer FL or a magnetic field of the direction different from that of the fixed magnetic layer FL is written to the free magnetic layer VL in a non-volatile manner.
In reading the data, the access transistor ATR is turned ON in response to activation of the read word line RWL. As a result, a sense current Is flows through a current path formed by the bit line BL, magnetic tunnel junction MTJ, access transistor ATR and ground voltage Vss. The sense current Is is supplied as a constant current from a not-shown control circuit.
The resistance value of the magnetic tunnel junction MTJ varies according to the relative relation of the magnetic field direction between the fixed magnetic layer FL and free magnetic layer VL. More specifically, in the case where the fixed magnetic layer FL and free magnetic layer VL have the same magnetic field direction, the magnetic tunnel junction MTJ has a smaller resistance value as compared to the case where both magnetic layers have different magnetic field directions.
Accordingly, in reading the data, a voltage level change at the magnetic tunnel junction MTJ due to the sense current Is varies according to the magnetic field direction stored in the free magnetic layer VL. Thus, by starting supply of the sense current Is after precharging the bit line BL to a prescribed voltage, the level of storage data in the MTJ memory cell can be read by monitoring a voltage level change on the bit line BL.
FIG. 90 is a conceptual diagram illustrating the data write operation to the MTJ memory cell.
Referring to FIG. 90, in writing the data, the read word line RWL is inactivated, and the access transistor ATR is turned OFF. In this state, a data write current for writing a magnetic field to the free magnetic layer VL is applied to the write word line WWL and bit line BL. The magnetic field direction of the free magnetic layer VL is determined by combination of the respective directions of the data write current flowing through the write word line WWL and bit line BL.
FIG. 91 is a conceptual diagram illustrating the relation between the respective directions of the data write current and magnetic field in the data write operation.
Referring to FIG. 91, a magnetic field Hx of the abscissa indicates the direction of a magnetic field H(WWL) produced by the data write current flowing through the write word line WWL. A magnetic field Hy of the ordinate indicates the direction of a magnetic field H(BL) produced by the data write current flowing through the bit line BL.
The magnetic field direction stored in the free magnetic layer VL is updated only when the sum of the magnetic fields H(WWL) and H(BL) reaches the region outside the asteroid characteristic line shown in the figure. In other words, the magnetic field direction stored in the free magnetic layer VL is not updated when a magnetic field corresponding to the region inside the asteroid characteristic line is applied.
Accordingly, in order to update the storage data of the magnetic tunnel junction MTJ by the data write operation, a current must be applied to both the write word line WWL and bit line BL. Once the magnetic field direction, i.e., the storage data, is stored in the magnetic tunnel junction MTJ, it is held therein in a non-volatile manner until a new data read operation is conducted.
The sense current Is flows through the bit line BL even in the data read operation. However, the sense current Is is generally set to a value that is smaller than the above-mentioned data write current by about one or two orders of magnitude. Therefore, it is less likely that the storage data in the MTJ memory cell is erroneously rewritten due to the sense current Is during the data read operation.
The above-mentioned technical documents disclose a technology of forming an MRAM device, a random access memory, with such MTJ memory cells integrated on a semiconductor substrate.
FIG. 92 is a conceptual diagram showing the MTJ memory cells arranged in rows and columns in an integrated manner.
Referring to FIG. 92, with the MTJ memory cells arranged in rows and columns on the semiconductor substrate, a highly integrated MRAM device can be realized. FIG. 92 shows the case where the MTJ memory cells are arranged in n rows by m columns (where n, m is a natural number).
As described before, the bit line BL, write word line WWL and read word line RWL must be provided for each MTJ memory cell. Accordingly, n write word lines WWL1 to WWLn, n read word lines RWL1 to RWLn, and m bit lines BL1 to BLm are required for the nxc3x97m MTJ memory cells. In other words, independent word lines must be provided for the read and write operations.
FIG. 93 is a diagram showing the structure of the MTJ memory cell formed on the semiconductor substrate.
Referring to FIG. 93, the access transistor ATR is formed in a p-type region PAR of a semiconductor main substrate SUB. The access transistor ATR has source/drain regions (n-type regions) 110, 120 and a gate 130. The source/drain region 110 is coupled to the ground voltage Vss through a metal wiring formed in a first metal wiling layer M1. A metal wiring formed in a second metal wiring layer M2 is used as the write word line WWL. The bit line BL is formed in a third metal wiring layer M3.
The magnetic tunnel junction MTJ is formed between the second metal wiring layer M2 of the write word line WWL and the third metal wiring layer M3 of the bit line BL. The source/drain region 120 of the access transistor ATR is electrically coupled to the magnetic tunnel junction MTJ through a metal film 150 formed in a contact hole, the first and second metal wiling layers M1 and M2, and a barrier metal 140. The barrier metal 140 is a buffer material for providing electrical coupling between the magnetic tunnel junction MTJ and metal wirings.
As described before, in the MTJ memory cell, the read word line RWL is provided independently of the write word line WWL. In addition, in writing the data, a data write current for generating a magnetic field equal to or higher than a predetermined value must be applied to the write word line WWL and bit line BL. Accordingly, the bit line BL and write word line WWL are each formed from a metal wiring.
On the other hand, the read word line RWL is provided in order to control the gate voltage of the access transistor ATR. Therefore, a current need not be actively applied to the read word line RWL. Accordingly, for the purpose of improving the integration degree, the read word line RWL is conventionally formed from a polysilicon layer, polycide structure, or the like in the same wiring layer as that of the gate 130 without forming an additional independent metal wiring layer.
Since a large number of wirings are required for the data read and write operations, integrating the MTJ memory cells on the semiconductor substrate results in increase in cell size due to the space required for such wirings.
Moreover, in order to integrate the MTJ memory cells, a reduced wiring pitch as well as an increased number of wiling layers are required, causing increase in manufacturing cost due to the complicated manufacturing process.
Furthermore, such increased numbers of wirings and wiring layers necessitate the use of so-called cross-point arrangement, i.e., the arrangement in which the MTJ memory cells are provided on the respective intersections of the word lines and bit lines, thereby making it difficult to ensure a sufficient margin of the read and write operations.
In writing the data, a relatively large data write current must be applied to the bit line BL. Moreover, the direction of the data write current must be controlled according to the level of write data, resulting in complicated circuitry for controlling the data write current.
It is an object of the present invention to achieve improved integration of an MRAM device having MTJ memory cells, by reducing the number of wirings provided in the entire memory array.
In summary, according to one aspect of the present invention, a thin film magnetic memory device includes a memory array, a plurality of read word lines, a plurality of data lines, a plurality of write word lines, and a plurality of reference voltage lines. The memory array has a plurality of magnetic memory cells arranged in rows and columns. Each of the plurality of magnetic memory cells includes a magnetic storage portion having a resistance value that varies according to a level of storage data to be written by first and second data write currents, and a memory cell selection gate for passing a data read current therethrough into the magnetic storage portion in a data read operation. The plurality of read word lines are provided corresponding to the respective rows of the magnetic memory cells, for actuating the corresponding memory cell selection gate according to a row selection result in the data read operation. The plurality of data lines are provided corresponding to the respective columns of the magnetic memory cells, for causing the first data write current and the data read current to flow therethrough in a data write operation and the data read operation, respectively. The plurality of write word lines are provided corresponding to the respective rows, and are selectively activated according to a row selection result in the data write operation so as to cause the second data write current to flow therethrough. The plurality of reference voltage lines are provided corresponding to either the respective rows or the respective columns, for supplying a reference voltage to be used in the data read operation. Adjacent magnetic memory cells share a corresponding one of at least one of the plurality of write word lines, the plurality of read word lines, the plurality of data lines and the plurality of reference voltage lines.
Accordingly, a primary advantage of the present invention is that the number of wirings provided in the memory array can be reduced in the thin film magnetic memory device including the magnetic memory cells for conducting the data read and write operations using the write word lines, read word lines, data lines and reference voltage lines. As a result, improved integration of the memory array as well as reduced chip area can be achieved.
According to another aspect of the present invention, a thin film magnetic memory device includes a memory array, a plurality of read word lines, a plurality of data lines, a plurality of write word lines, and a word line current control circuit. The memory array has a plurality of magnetic memory cells arranged in rows and columns. Each of the plurality of magnetic memory cells includes a magnetic storage portion having a resistance value that varies according to a level of storage data to be written by first and second data write currents, and a memory cell selection gate for passing a data read current therethrough into the magnetic storage portion in a data read operation. The plurality of read word lines are provided corresponding to the respective rows of the magnetic memory cells, for actuating the corresponding memory cell selection gate according to a row selection result in the data read operation. The plurality of data lines are provided corresponding to the respective columns of the magnetic memory cells, for causing the first data write current and the data read current to flow therethrough in a data write operation and the data read operation, respectively. The plurality of write word lines are provided corresponding to the respective rows, and are selectively activated according to a row selection result in the data write operation so as to cause the second data write current to flow therethrough. The word line current control circuit couples the plurality of write word lines to a reference voltage that is used in the data read operation. Adjacent magnetic memory cells share a corresponding one of at least one of the plurality of write word lines, the plurality of read word lines and the plurality of data lines.
Accordingly, the number of wirings can be reduced that are provided in the memory array including the magnetic memory cells for conducting the data read and write operations using the write word lines, read word lines and data lines. As a result, improved integration of the memory array as well as reduced chip area can be achieved.
According to still another aspect of the present invention, a thin film magnetic memory device includes a memory array, a plurality of read word lines, a plurality of signal lines, a read/write control circuit, a plurality of write word lines, and a plurality of control switches. The memory array has a plurality of magnetic memory cells arranged in rows and columns. Each of the plurality of magnetic memory cells includes a magnetic storage portion having a resistance value that varies according to a level of storage data to be written by first and second data write currents, and a memory cell selection gate for passing a data read current therethrough into the magnetic storage portion in a data read operation. The plurality of read word lines are provided corresponding to the respective rows of the magnetic memory cells, for actuating the corresponding memory cell selection gate according to a row selection result in the data read operation. The plurality of signal lines are provided corresponding to the respective columns of the magnetic memory cells. Adjacent magnetic memory cells in the row direction share a corresponding one of the plurality of signal lines. The read/write control circuit supplies the first data write current and the data read current to the signal lines in a data write operation and the data read operation, respectively. The plurality of write word lines are provided corresponding to the respective rows, and are selectively activated according to a row selection result in the data write operation so as to cause the second data write current to flow therethrough. The plurality of control switches are provided respectively corresponding to the plurality of signal lines, for electrically coupling a reference voltage that is used in the data read operation to a corresponding one of the plurality of signal lines. The plurality of control switches each couples a selected one of two signal lines corresponding to the respective magnetic memory cells to the reference voltage, according to the row selection result.
In such a thin film magnetic memory device, the magnetic memory cells for conducting the data read and write operations using the write word lines, read word lines, and common lines functioning both as data line and reference voltage line can be arranged in the memory array with a reduced number of common lines. As a result, improved integration of the memory array as well as reduced chip area can be achieved.
According to yet another aspect of the present invention, a thin film magnetic memory device includes a memory array, a plurality of write word lines, a plurality of read word lines, a plurality of write data lines, and a plurality of read data lines. The memory array has a plurality of magnetic memory cells arranged in rows and columns. Each of the plurality of magnetic memory cells includes a magnetic storage portion having a resistance value that varies according to a level of storage data to be written when a data write magnetic field applied by first and second data write currents is larger than a predetermined magnetic field, and a memory cell selection gate for passing a data read current therethrough into the magnetic storage portion in a data read operation. The plurality of write word lines are provided corresponding to the respective rows of the magnetic memory cells, and are selectively activated according to a row selection result in a data write operation so as to cause the first data write current to flow therethrough. The plurality of read word lines are provided corresponding to the respective rows, for actuating the corresponding memory cell selection gate according to a row selection result in the data read operation. The plurality of write data lines are provided corresponding to the respective columns of the magnetic memory cells, for causing the second data write current to flow therethrough in the data write operation. The plurality of read data lines are provided corresponding to the respective columns, for causing the data read current to flow therethrough in the data read operation. Adjacent magnetic memory cells share a corresponding one of at least one of the plurality of write word lines, the plurality of read word lines, the plurality of read data lines and the plurality of write data lines.
In such a thin film magnetic memory device, the number of wirings can be reduced that are provided in the memory array including the magnetic memory cells for conducting the data read and write operations using the write word lines, read word lines, write data lines and read data lines. As a result, improved integration of the memory array as well as reduced chip area can be achieved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.